1. Field of the Invention
This invention relates generally to semiconductor memory devices, and more particularly to an internal source voltage generator for a semiconductor memory device.
2. Description of the Related Art
A semiconductor memory device typically employs an internal source voltage generating circuit which generates an internal source voltage signal at a stable voltage level regardless of variations in an external source voltage signal. FIGS. 1-2 illustrate the structure and operation of a prior art internal source voltage signal generating circuit. Referring to FIG. 2, when the voltage of the external source voltage signal Vext is in a low voltage range between zero volts and Vno, the voltage of the internal source voltage signal Vint increases in proportion to the voltage of Vext. As Vext increases through a normal operation range (between Vno and Vsm), the circuit of FIG. 1 clamps the voltage of Vint at the level Vno and maintains it at that voltage level until Vext exceeds Vsm. When the voltage level of Vext increases beyond Vsm, the voltage of Vint increases as Vext increases.
The operation of the prior art internal source voltage signal generating circuit will now be explained in more detail with reference to FIG. 1. As the voltage of Vext increases from zero volts to Vno, which is the normal operating voltage, the voltage of Vint increases with, and remains equal to, the voltage of Vext. A boosted voltage signal VPP is generated by boosting the internal source voltage signal Vint. The signal VPP is applied to a word line coupled to a memory cell. The voltage level Vwl corresponds to the level of the voltage boosted by a threshold voltage Vt of an access transistor. When the voltage level of Vext enters the normal operating region, the level of the voltage Vwl is clamped by 2 Vt by means of PMOS transistors 105 and 106 and maintained at a fixed level. The voltage level of the boosted voltage signal VPP is maintained at a fixed difference from the voltage level of Vint.
When the voltage level of the external source voltage signal Vext enters a stress operating range, which is greater than Vsm, the voltage level of the signals Vint and VPP increase (with a fixed difference therebetween) as the voltage levels of Vext increases regardless of whether the memory device is in a normal operating mode or a stress operating mode.
To assure the reliability of a semiconductor chip when the external voltage signal Vext is in the stress operating range, a burn-in test for screening the chip must be performed when the chip is in a test mode. To perform such a test, an internal source voltage signal having a voltage higher than the normal operating voltage Vno must be applied to the interior of the semiconductor chip to apply enough stress for proper testing.
The two operating voltage ranges used in the interior of a semiconductor chip are the clamping range (from Vno to Vsm) and the stress range (above Vsm). The voltage of Vint is set internally by the circuit of FIG. 1 which operates to supply a stable voltage in the normal operation range as shown in FIG. 2. The voltage of Vint increases as the voltage of the external source voltage Vext increases in the stress operating range so as to stress the interior of the chip. The operating range of the internal source voltage signal Vint is determined by the voltage of the external source voltage signal Vext which is applied to the chip. I.e., when the voltage of Vext is in the normal range between Vno and Vsm, the voltage of Vint is maintained at a stable level of Vno, and when the voltage of Vext is increased to the stress operating range above Vsm, the voltage of Vint increases as the voltage of Vext increases.
In a memory cell structure which uses an NMOS transistor as the access transistor (for example, a typical DRAM structure) a boost voltage signal VPP is required in the interior of the semiconductor chip because the voltage of the word line as a gate node of the access transistor must be high enough to reciprocally transmit data between bit lines and storage nodes. The voltage of VPP is typically Vint plus 1 Vt. Because the voltage of the boost signal VPP is similar to that of Vint with the exception of the level difference, it too can be divided into a normal operation range and a stress operation range.
However, this creates a problem in that, as the voltage level of Vint increases in the stress operation range, the voltage level of VPP increases to the extent that it causes the chip to malfunction. Another disadvantage of the prior art is that, during a normal operation mode, if Vext increases into the stress operating range, the increased voltage of VPP can reduce the lifetime of the chip due to the stress applied directly to the memory cells.
Accordingly, a need remains for a technique for overcoming the disadvantages of the prior art.